Optimized Implementation of GHz ARM Cortex-A9 Processor - High Performance, with Low Power
Synopsys

Both mobile and tethered devices are requiring increased performance with decreased power consumption. In this session. we'll present how the combination of optimized methodology. tools and physical IP can address these needs. With many design implementations. getting the last 10% performance increase can take 80% or more of the total effort. This classic dilemma wreaks havoc on design schedules and causes the risk averse to limit such uncertain activities. Realizing this. Synopsys and ARM have partnered in a 2-year series of implementation case studies across methodologies. libraries. and process technologies on the ARM Cortex™-A9 processor design. In this paper. we discuss our latest case study targeted at pushing performance for the ARM Cortex-A9 core using early access ARM Physical IP libraries and memories for the Common Platform™ 32nm low-power foundry process and the Synopsys Galaxy™ Implementation Platform. The paper describes using some of the latest 2009.06 DC Graphical and IC Compiler capabilities together with a highly tuned set of user constraints. delivering surprising performance. power and area results. The techniques discussed here could be applicable to any high-performance design. Key techniques covered include: library subset usage scenarios. delay performance vs. cell area tradeoffs. cell placement density vs. floorplan dimension tuning. placement bounds overrides for clock and data paths. multi-scenario design optimization. leakage optimization techniques. signoff optimization between IC Compiler and Prime Time. as well as the usage of the latest clock tree synthesis and clock mesh capabilities together with intelligent user clock constraints. For each technique. we examine the performance advantage offered and ease of convergence as well as the schedule/turnaround time cost. The authors have extensive experience with leading-edge implementations of ARM processor cores. pioneering new techniques and methodologies as well as collaborating to optimize methodology. tools. and IP together for high performance/low power implementations.

Daniel Biset , Principal Application Engineer
Daniel is principal application engineer and has been with Synopsys for more than 13 years. He has extensive experience and an expert on high performance and low power IC design implementation. He has been working with ARM in developing implementation methodology for high performance low power application processors including Cortex-A8 and A9.