Solving Common Power Management Verification Issues in ARM-Based SoCs
Mimasic, Synopsys, Conexant

Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs such as SoCs using ARM Cortex cores. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created. We take a look at some of the main power management verification problems found in such SoCs including issues with reset out of wake up, power connectivity, domain isolation and retention, incorrect power sequencing protocol, level shifting errors, and power state management. We will go over details of each of these issues along with solutions to these issues using verification strategy that involved power-aware simulation, rule-based structural checking, and formal tools.

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