High-Performance, Lower-Power, Reduced Route Architecture for the AMBA 3 AXI On-Chip Interconnect
Synopsys

In a typical system the bandwidth requirements for each interconnecting master and slave varies widely. Some master-slave links have high bandwidth requirements, while others have low latency requirements. Faced with growing demands on system performance it becomes increasingly important to be able to effectively tune the bandwidth allocation for each master-slave link in the system. This presentation details an On-Chip-Bus architecture that enables the setting of bandwidth allocation at each arbitration point with reduced On-Chip-Bus area/power and routing for predefined low performance links.

Fred Roberts, Senior Corperate Applications Engineer
Fred Roberts is a Senior Corporate Applications Engineer at Synopsys, working with DesignWare Synthesizable IP for AMBA 2.0 and AMBA 3.0 AXI. Prior to helping Synopsys users, Fred served as a member of the R&D teams for the USB, USB OTG, and Wireless USB cores. Fred has been with Synopsys since early 2003. Prior to Synopsys, Fred worked at Qualis Design (Acquired by Synopsys) developing and supporting Verification IP for USB.

Michael Posner, Manager
Michael Posner joined Synopsys in 1994 and is currently a Product Manager for Synopsys' DesignWare® IP Solutions for SATA & AMBA. Before this role he was an application consultant and technical marketing manager at Synopsys. He holds a Bachelors Degree in Electronic and Computer Engineering from the University of Brighton, England.